/**
 @file sys_usw_mcu.h

 @author  Copyright (C) 2011 Centec Networks Inc.  All rights reserved.

 @date 2011-11-9

 @version v2.0

*/

#ifndef _SYS_USW_MCU_H
#define _SYS_USW_MCU_H
#ifdef __cplusplus
extern "C" {
#endif

/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_chip.h"
#include "ctc_const.h"


#define SYS_USW_DATA_MEM_ENTRY_NUM    15360
#define SYS_USW_PROG_MEM_ENTRY_NUM    16384
#define SYS_USW_DATA_MEM_BASE_ADDR0   0x000a0000
#define SYS_USW_PROG_MEM_BASE_ADDR0   0x00090000
#define SYS_USW_DATA_MEM_BASE_ADDR1   0x00060000
#define SYS_USW_PROG_MEM_BASE_ADDR1   0x00050000

/* #1, MCU global info */
#define SYS_USW_MCU_GLB_INFO_BASE_ADDR  (SYS_USW_DATA_MEM_BASE_ADDR0 + 0x0)
#define SYS_USW_MCU_VER_BASE_ADDR       (SYS_USW_MCU_GLB_INFO_BASE_ADDR + 0x0)    /* 4 Bytes */
#define SYS_USW_MCU_GLB_ON_BASE_ADDR    (SYS_USW_MCU_GLB_INFO_BASE_ADDR + 0x4)    /* 4 Bytes */

/* #2, MCU port data structure */
#define SYS_USW_MCU_PORT_DS_BASE_ADDR   (SYS_USW_DATA_MEM_BASE_ADDR0 + 1*0x400)
#define SYS_USW_MCU_PORT_ALLOC_BYTE     16

/* #3, MCU port other cfg/status */
#define SYS_USW_MCU_PORT_OTHER_BASE_ADDR   (SYS_USW_DATA_MEM_BASE_ADDR0 + 2*0x400)
#define SYS_USW_MCU_PORT_ON_BASE_ADDR      (SYS_USW_MCU_PORT_OTHER_BASE_ADDR + 0x0)   /* 64 Bytes, 1 Byte per port */
#define SYS_USW_MCU_PORT_LOG_BASE_ADDR     (SYS_USW_MCU_PORT_OTHER_BASE_ADDR + 0x40)  /* 256 Bytes, 4 Bytes per port */

/* #4, MCU global info dump unitest */
#define SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR   (SYS_USW_DATA_MEM_BASE_ADDR0 + 6*0x400)
//#define SYS_USW_MCU_UT_VER_BASE_ADDR        (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x0)
#define SYS_USW_MCU_UT_GLB_ON_BASE_ADDR     (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x0)
#define SYS_USW_MCU_UT_RUNLOOP_BASE_ADDR    (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x4)
#define SYS_USW_MCU_UT_15GFAIL_BASE_ADDR    (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x8)
#define SYS_USW_MCU_UT_28GFAIL_BASE_ADDR    (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0xc)
#define SYS_USW_MCU_UT_LOCK_TIMES           (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x10)
#define SYS_USW_MCU_UT_WADN_RUN_TEST        (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x14)
#define SYS_USW_MCU_UT_WAUP_RUN_TEST        (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x18)
#define SYS_USW_MCU_UT_LOCK_FAIL_TIMES      (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x1c)
#define SYS_USW_MCU_UT_UNLOCK_TIMES         (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x20)
#define SYS_USW_MCU_UT_UNLOCK_FAIL_TIMES    (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x24)
#define SYS_USW_MCU_WA_UP_PORT              (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x2c)
#define SYS_USW_MCU_WA_DN_PORT              (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x30)
#define SYS_USW_MCU_CURR_ROUND              (SYS_USW_MCU_UT_GLB_INFO_BASE_ADDR + 0x34)

/* #5, MCU port data structure dump unitest */
#define SYS_USW_MCU_UT_PORT_DS_BASE_ADDR    (SYS_USW_DATA_MEM_BASE_ADDR0 + 7*0x400)

/* #6, MCU port unittest */
#define SYS_USW_MCU_UT_BASE_ADDR            (SYS_USW_DATA_MEM_BASE_ADDR0 + 8*0x400)
#define SYS_USW_MCU_UT_PORT_BASE_ADDR(x)    (SYS_USW_MCU_UT_BASE_ADDR + 256*x)  /* 256 Bytes per port */
#define SYS_USW_MCU_UT_PORT_ON_ACK_OFST      0x0    /* 4 Bytes per port */
#define SYS_USW_MCU_UT_PORT_DBG_ON_OFST      0x4    /* 4 Bytes per port */
#define SYS_USW_MCU_UT_PORT_DBG_ON_ACK_OFST  0x8    /* 4 Bytes per port */
#define SYS_USW_MCU_UT_PORT_SIGDET_OFST      0xc    /* 4 Bytes per port */
#define SYS_USW_MCU_UT_PORT_LINK_STA_OFST    0x10   /* 4 Bytes per port */

#define SYS_USW_MCU_UT_PORT_CODEERR_ADDR_OFST   0x14   /* 20 Bytes per port, see _sys_usw_get_code_err_tbl_addr() */
#define SYS_USW_MCU_UT_PORT_LINK_ADDR_OFST      0x28   /* 4 Bytes per port */
#define SYS_USW_MCU_UT_PORT_PCS_ADDR_OFST       0x2c   /* 12 Bytes per port (addr + val + val)*/
#define SYS_USW_MCU_UT_PORT_FEC_ADDR_OFST       0x38   /* 12 Bytes per port (addr + val + val)*/
#define SYS_USW_MCU_UT_PORT_NETTX_CRFEDIT1      0x44   /* 4 Bytes per port */
#define SYS_USW_MCU_UT_PORT_NETTX_CRFEDIT2      0x48   /* 4 Bytes per port */

#define SYS_USW_MCU_UT_PORT_IGN_FT_OFST         0x4c   /* 12 Bytes per port(addr + val + val) */

/* #7, MCU WA test */
#define SYS_USW_MCU_WA_BASE_ADDR            (SYS_USW_DATA_MEM_BASE_ADDR0 + 24*0x400)
#define SYS_USW_MCU_WA_ROUND1_BASE_ADDR      SYS_USW_MCU_WA_BASE_ADDR


/*#################################################### TM start ##################################################*/
 /*TM macros*/
#define SYS_TSINGMA_MCU_MAX_NUM 4
#define SYS_TSINGMA_MCU_MAX_PORT_PER_CORE   32
#define SYS_TSINGMA_MCU_MAX_SERDES_PER_CORE 8
#define SYS_TSINGMA_MCU_WORD_BYTE           4
#define SYS_TSINGMA_MCU_PORT_ALLOC_BYTE     (4*SYS_TSINGMA_MCU_WORD_BYTE)
#define SYS_TSINGMA_MCU_SERDES_ALLOC_BYTE   (8*SYS_TSINGMA_MCU_WORD_BYTE)
 /*#define SYS_TSINGMA_MCU_DATA_MEM_LEN        0x700        //bytes*/
#define SYS_TSINGMA_MCU_SUP_PROG_MEM_0_ADDR 0x004d0000   /*McuSupProgMem0*/
#define SYS_TSINGMA_MCU_SUP_PROG_MEM_1_ADDR 0x00550000   /*McuSupProgMem1*/
#define SYS_TSINGMA_MCU_SUP_PROG_MEM_2_ADDR 0x005d0000   /*McuSupProgMem2*/
#define SYS_TSINGMA_MCU_SUP_PROG_MEM_3_ADDR 0x002d0000   /*McuSupProgMem3*/
#define SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR 0x004e0000   /*McuSupDataMem0*/
#define SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR 0x00560000   /*McuSupDataMem1*/
#define SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR 0x005e0000   /*McuSupDataMem2*/
#define SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR 0x002e0000   /*McuSupDataMem3*/
#define SYS_TSINGMA_MCU_DATA_MEM_LEN        0xc800       /*bytes*/

/*
                           Tsingma MCU data memory structure
+----------------------------+---------------------------+----------------------------+
|    MCU core global info    |  port info (max 32 port)  | serdes info (max 8 serdes) |
+-------------------------------------------------------------------------------------+
+        1024 bytes          +       512 bytes           +         256 bytes          +
base addr                    0x400                       0x600                        0x700
*/
#define SYS_TSINGMA_MCU_0_CORE_ID_ADDR          (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x0)        /* MCU core id, 4 Bytes */
#define SYS_TSINGMA_MCU_0_VERSION_BASE_ADDR     (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x4)        /* MCU version info, 4 Bytes */
#define SYS_TSINGMA_MCU_0_SWITCH_CTL_ADDR       (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x8)        /* MCU core switch control, 4 Byte */
#define SYS_TSINGMA_MCU_0_SWITCH_STAT_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0xc)        /* MCU core switch status, 4 Byte */
#define SYS_TSINGMA_MCU_0_QM_CHOICE_ADDR        (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x10)       /* MCU port mac qm choice, g_qm_choice, 4 Byte */
#define SYS_TSINGMA_MCU_0_SW_MODE_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x20)       /* Software mode control, refer to mcu_sw_mode_t */
#define SYS_TSINGMA_MCU_0_TEST_MODE_CTL_ADDR    (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x24)       /* test mode control, written by CPU, read only for MCU */
#define SYS_TSINGMA_MCU_0_TEST_MODE_STAT_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x28)       /* test mode status, refer to mcu_test_mode_stat_t */
#define SYS_TSINGMA_MCU_0_TEST_LOCK_SUCC_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x2c)       /* test mode, lock success counter */
#define SYS_TSINGMA_MCU_0_TEST_LOCK_FAIL_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x30)       /* test mode, lock fail counter */
#define SYS_TSINGMA_MCU_0_TEST_MCU_LOCK_CNT     (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x34)       /* test mode, mcu lock number */
#define SYS_TSINGMA_MCU_0_DELAY_CYCLE_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x38)       /* Delay cycle */
#define SYS_TSINGMA_MCU_0_DBG_LOG_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x3c)       /* Debug log control */
#define SYS_TSINGMA_MCU_0_ISCAN_MODE_CTL        (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x40)       /* fast iscan mode control, default 0 (center height) */
#define SYS_TSINGMA_MCU_0_INIT_FFE_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x44)       /* LT init FFE: flag[7:0], txmg[15:8], adv[23:16], dly[31:24]*/
#define SYS_TSINGMA_MCU_0_RX_EQ_LT_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x48)       /* RX adjust after LT, 0-no RX eq, 1-RX eq after LT */
#define SYS_TSINGMA_MCU_0_ISCAN_MIN_VAL_THD     (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x4c)       /* minimun iscan fine value, any value less than that is equal to 0 */
#define SYS_TSINGMA_MCU_0_DFE_OPR_IND           (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x50)       /* DFE operation indicator, 0-no operation, 1-DFE enable, 2-DFE unhold */
#define SYS_TSINGMA_MCU_0_EYE_DRIFT_TOLERANCE   (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x64)       /* LT eye drift tolerance*/
#define SYS_TSINGMA_MCU_0_LT_RESTART_LANE       (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 0x68)       /* LT restart flag, bit 0~7 for lane 0~7*/
#define SYS_TSINGMA_MCU_0_PORT_INFO_BASE_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_0_ADDR + 1*0x400)    /* port info address, 16 bytes/port */
#define SYS_TSINGMA_MCU_0_SERDES_INFO_BASE_ADDR (SYS_TSINGMA_MCU_0_PORT_INFO_BASE_ADDR + 0x200)    /* serdes info address, 32 bytes/serdes */

#define SYS_TSINGMA_MCU_1_CORE_ID_ADDR          (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x0)        /* MCU core id, 4 Bytes */
#define SYS_TSINGMA_MCU_1_VERSION_BASE_ADDR     (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x4)        /* MCU version info, 4 Bytes */
#define SYS_TSINGMA_MCU_1_SWITCH_CTL_ADDR       (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x8)        /* MCU core switch control, 4 Byte */
#define SYS_TSINGMA_MCU_1_SWITCH_STAT_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0xc)        /* MCU core switch status, 4 Byte */
#define SYS_TSINGMA_MCU_1_QM_CHOICE_ADDR        (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x10)       /* MCU port mac qm choice, g_qm_choice, 4 Byte */
#define SYS_TSINGMA_MCU_1_SW_MODE_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x20)       /* Software mode control, refer to mcu_sw_mode_t */
#define SYS_TSINGMA_MCU_1_TEST_MODE_CTL_ADDR    (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x24)       /* test mode control, written by CPU, read only for MCU */
#define SYS_TSINGMA_MCU_1_TEST_MODE_STAT_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x28)       /* test mode status, refer to mcu_test_mode_stat_t */
#define SYS_TSINGMA_MCU_1_TEST_LOCK_SUCC_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x2c)       /* test mode, lock success counter */
#define SYS_TSINGMA_MCU_1_TEST_LOCK_FAIL_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x30)       /* test mode, lock fail counter */
#define SYS_TSINGMA_MCU_1_TEST_MCU_LOCK_CNT     (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x34)       /* test mode, mcu lock number */
#define SYS_TSINGMA_MCU_1_DELAY_CYCLE_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x38)       /* Delay cycle */
#define SYS_TSINGMA_MCU_1_DBG_LOG_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x3c)       /* Debug log control */
#define SYS_TSINGMA_MCU_1_ISCAN_MODE_CTL        (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x40)       /* fast iscan mode control, default 0 (center height) */
#define SYS_TSINGMA_MCU_1_INIT_FFE_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x44)       /* LT init FFE: flag[7:0], txmg[15:8], adv[23:16], dly[31:24]*/
#define SYS_TSINGMA_MCU_1_RX_EQ_LT_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x48)       /* RX adjust after LT, 0-no RX eq, 1-RX eq after LT */
#define SYS_TSINGMA_MCU_1_ISCAN_MIN_VAL_THD     (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x4c)       /* minimun iscan fine value, any value less than that is equal to 0 */
#define SYS_TSINGMA_MCU_1_DFE_OPR_IND           (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x50)       /* DFE operation indicator, 0-no operation, 1-DFE enable, 2-DFE unhold */
#define SYS_TSINGMA_MCU_1_EYE_DRIFT_TOLERANCE   (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x64)       /* LT eye drift tolerance*/
#define SYS_TSINGMA_MCU_1_LT_RESTART_LANE       (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 0x68)       /* LT restart flag, bit 0~7 for lane 0~7*/
#define SYS_TSINGMA_MCU_1_PORT_INFO_BASE_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_1_ADDR + 1*0x400)    /* port info address, 16 bytes/port */
#define SYS_TSINGMA_MCU_1_SERDES_INFO_BASE_ADDR (SYS_TSINGMA_MCU_1_PORT_INFO_BASE_ADDR + 0x200)    /* serdes info address, 32 bytes/serdes */

#define SYS_TSINGMA_MCU_2_CORE_ID_ADDR          (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x0)        /* MCU core id, 4 Bytes */
#define SYS_TSINGMA_MCU_2_VERSION_BASE_ADDR     (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x4)        /* MCU version info, 4 Bytes */
#define SYS_TSINGMA_MCU_2_SWITCH_CTL_ADDR       (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x8)        /* MCU core switch control, 4 Byte */
#define SYS_TSINGMA_MCU_2_SWITCH_STAT_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0xc)        /* MCU core switch status, 4 Byte */
#define SYS_TSINGMA_MCU_2_QM_CHOICE_ADDR        (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x10)       /* MCU port mac qm choice, g_qm_choice, 4 Byte */
#define SYS_TSINGMA_MCU_2_SW_MODE_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x20)       /* Software mode control, refer to mcu_sw_mode_t */
#define SYS_TSINGMA_MCU_2_TEST_MODE_CTL_ADDR    (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x24)       /* test mode control, written by CPU, read only for MCU */
#define SYS_TSINGMA_MCU_2_TEST_MODE_STAT_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x28)       /* test mode status, refer to mcu_test_mode_stat_t */
#define SYS_TSINGMA_MCU_2_TEST_LOCK_SUCC_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x2c)       /* test mode, lock success counter */
#define SYS_TSINGMA_MCU_2_TEST_LOCK_FAIL_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x30)       /* test mode, lock fail counter */
#define SYS_TSINGMA_MCU_2_TEST_MCU_LOCK_CNT     (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x34)       /* test mode, mcu lock number */
#define SYS_TSINGMA_MCU_2_DELAY_CYCLE_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x38)       /* Delay cycle */
#define SYS_TSINGMA_MCU_2_DBG_LOG_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x3c)       /* Debug log control */
#define SYS_TSINGMA_MCU_2_ISCAN_MODE_CTL        (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x40)       /* fast iscan mode control, default 0 (center height) */
#define SYS_TSINGMA_MCU_2_INIT_FFE_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x44)       /* LT init FFE: flag[7:0], txmg[15:8], adv[23:16], dly[31:24]*/
#define SYS_TSINGMA_MCU_2_RX_EQ_LT_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x48)       /* RX adjust after LT, 0-no RX eq, 1-RX eq after LT */
#define SYS_TSINGMA_MCU_2_ISCAN_MIN_VAL_THD     (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x4c)       /* minimun iscan fine value, any value less than that is equal to 0 */
#define SYS_TSINGMA_MCU_2_DFE_OPR_IND           (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x50)       /* DFE operation indicator, 0-no operation, 1-DFE enable, 2-DFE unhold */
#define SYS_TSINGMA_MCU_2_EYE_DRIFT_TOLERANCE   (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x64)       /* LT eye drift tolerance*/
#define SYS_TSINGMA_MCU_2_LT_RESTART_LANE       (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 0x68)       /* LT restart flag, bit 0~7 for lane 0~7*/
#define SYS_TSINGMA_MCU_2_PORT_INFO_BASE_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_2_ADDR + 1*0x400)    /* port info address, 16 bytes/port */
#define SYS_TSINGMA_MCU_2_SERDES_INFO_BASE_ADDR (SYS_TSINGMA_MCU_2_PORT_INFO_BASE_ADDR + 0x200)    /* serdes info address, 32 bytes/serdes */

#define SYS_TSINGMA_MCU_3_CORE_ID_ADDR          (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x0)        /* MCU core id, 4 Bytes */
#define SYS_TSINGMA_MCU_3_VERSION_BASE_ADDR     (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x4)        /* MCU version info, 4 Bytes */
#define SYS_TSINGMA_MCU_3_SWITCH_CTL_ADDR       (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x8)        /* MCU core switch control, 4 Byte */
#define SYS_TSINGMA_MCU_3_SWITCH_STAT_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0xc)        /* MCU core switch status, 4 Byte */
#define SYS_TSINGMA_MCU_3_QM_CHOICE_ADDR        (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x10)       /* MCU port mac qm choice, g_qm_choice, 4 Byte */
#define SYS_TSINGMA_MCU_3_SW_MODE_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x20)       /* Software mode control, refer to mcu_sw_mode_t */
#define SYS_TSINGMA_MCU_3_TEST_MODE_CTL_ADDR    (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x24)       /* test mode control, written by CPU, read only for MCU */
#define SYS_TSINGMA_MCU_3_TEST_MODE_STAT_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x28)       /* test mode status, refer to mcu_test_mode_stat_t */
#define SYS_TSINGMA_MCU_3_TEST_LOCK_SUCC_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x2c)       /* test mode, lock success counter */
#define SYS_TSINGMA_MCU_3_TEST_LOCK_FAIL_CNT    (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x30)       /* test mode, lock fail counter */
#define SYS_TSINGMA_MCU_3_TEST_MCU_LOCK_CNT     (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x34)       /* test mode, mcu lock number */
#define SYS_TSINGMA_MCU_3_DELAY_CYCLE_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x38)       /* Delay cycle */
#define SYS_TSINGMA_MCU_3_DBG_LOG_CTL_ADDR      (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x3c)       /* Debug log control */
#define SYS_TSINGMA_MCU_3_ISCAN_MODE_CTL        (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x40)       /* fast iscan mode control, default 0 (center height) */
#define SYS_TSINGMA_MCU_3_INIT_FFE_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x44)       /* LT init FFE: flag[7:0], txmg[15:8], adv[23:16], dly[31:24]*/
#define SYS_TSINGMA_MCU_3_RX_EQ_LT_ADDR         (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 0x48)       /* RX eq before LT flag, 0-no RX eq, 1-RX eq before LT */
#define SYS_TSINGMA_MCU_3_PORT_INFO_BASE_ADDR   (SYS_TSINGMA_MCU_SUP_DATA_MEM_3_ADDR + 1*0x400)    /* port info address, 16 bytes/port */
#define SYS_TSINGMA_MCU_3_SERDES_INFO_BASE_ADDR (SYS_TSINGMA_MCU_3_PORT_INFO_BASE_ADDR + 0x200)    /* serdes info address, 32 bytes/serdes */





/*#################################################### USW SINCE AT ##################################################*/

#define MCU_GLB_INFO_MCU_ID                  0x00
#define MCU_GLB_INFO_DBG_LOG_BASE_ADDR       0x04
#define MCU_GLB_INFO_DBG_LOG_LEN             0x08
#define MCU_GLB_INFO_MSG_PRIORITY_NUM        0x0c
#define MCU_GLB_INFO_MSG_ID_NUM              0x10
#define MCU_GLB_INFO_MSG_BUF_BASE_ADDR       0x14
#define MCU_GLB_INFO_MSG_SYNC_BUF_LEN        0x18
#define MCU_GLB_INFO_MSG_ASYNC_BUF_LEN       0x20
#define MCU_GLB_INFO_DBG_LOG_CTL             0x24
#define MCU_GLB_INFO_DBG_LOG_PTR             0x28
#define MCU_GLB_INFO_SYN_STATUS              0x2c
#define MCU_GLB_INFO_ANLT_SM_AN_TIMEOUT      0x30
#define MCU_GLB_INFO_ANLT_SM_LT_TIMEOUT      0x34
#define MCU_GLB_INFO_ANLT_SM_LINK_UP_TIMEOUT 0x38
#define MCU_GLB_INFO_LINK_ADJUST_EN          0x3c
#define MCU_GLB_INFO_PORT_MAPPING_BASE       0x40
#define MCU_GLB_INFO_MAC_STATS_BASE_ADDR     0x800
#define MCU_GLB_INFO_MAC_STATS_BUF_LEN       0x1400
#define GLB_INFO_VER_DATE                    0x100
#define GLB_INFO_VER_COMMIT                  0x104
#define GLB_INFO_MAIN_THREAD_STACK_ADDR      0x108
#define GLB_INFO_MAIN_THREAD_STACK_SIZE      0x10c
#define MCU_GLB_INFO_INTR_CNT_STATS_BASE_ADDR 0x200

/* mcu hardware lock start */
#define MCU_HW_LOCK_MAX_GRANT_ID      8
#define MCU_HW_LOCK_MAX_GRAND_BIT_ID  32
#define DMPS_HW_LOCK_GRANT_ID         0

enum dmps_hw_lock_grand_bit_e
{
    DMPS_HW_LOCK_GRAND_BIT_0   = 0,   /* port mapping        */
    DMPS_HW_LOCK_GRAND_BIT_1   = 1,   /* serdes reg io hss_0 */
    DMPS_HW_LOCK_GRAND_BIT_2   = 2,   /* serdes reg io hss_1 */
    DMPS_HW_LOCK_GRAND_BIT_3   = 3,   /* dmps msg            */
    DMPS_HW_LOCK_GRAND_BIT_4   = 4,   /* cl73 reg io hss_0   */
    DMPS_HW_LOCK_GRAND_BIT_5   = 5,   /* cl73 reg io hss_1   */
    DMPS_HW_LOCK_GRAND_BIT_6   = 6,   /* m2c intr            */
    DMPS_HW_LOCK_GRAND_BIT_MAX = 32,
};
typedef enum dmps_hw_lock_grand_bit_e dmps_hw_lock_grand_bit_t;
#define MCU_HW_LOCK(lchip, core_id, core_mcu_id, grand_id, bit)                                             \
do {                                                                                                        \
    if (NULL != MCHIP_DMPS(lchip)->mcu_hw_lock)                                                             \
    {                                                                                                       \
        CTC_ERROR_RETURN(MCHIP_DMPS(lchip)->mcu_hw_lock(lchip, core_id, core_mcu_id, grand_id, bit));       \
    }                                                                                                       \
} while (0)                                                                                                           \


#define MCU_HW_UNLOCK(lchip, core_id, core_mcu_id, grand_id, bit)                                           \
do {                                                                                                        \
    if (NULL != MCHIP_DMPS(lchip)->mcu_hw_unlock)                                                           \
    {                                                                                                       \
        CTC_ERROR_RETURN(MCHIP_DMPS(lchip)->mcu_hw_unlock(lchip, core_id, core_mcu_id, grand_id, bit));     \
    }                                                                                                       \
} while (0)

#define PORT_MAPPING_HW_LOCK(lchip, core_id, core_mcu_id)   MCU_HW_LOCK(lchip,   core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, DMPS_HW_LOCK_GRAND_BIT_0)
#define PORT_MAPPING_HW_UNLOCK(lchip, core_id, core_mcu_id) MCU_HW_UNLOCK(lchip, core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, DMPS_HW_LOCK_GRAND_BIT_0)

#define SERDES_REG_IO_HW_LOCK(lchip, core_id, core_mcu_id, hss_grp)  MCU_HW_LOCK(lchip, core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, \
                                                                           ((hss_grp == 0) ? DMPS_HW_LOCK_GRAND_BIT_1 : DMPS_HW_LOCK_GRAND_BIT_2))

#define SERDES_REG_IO_HW_UNLOCK(lchip, core_id, core_mcu_id, hss_grp) MCU_HW_UNLOCK(lchip, core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, \
                                                                            ((hss_grp == 0) ? DMPS_HW_LOCK_GRAND_BIT_1 : DMPS_HW_LOCK_GRAND_BIT_2))

#define DMPS_MSG_HW_LOCK(lchip, core_id, core_mcu_id)   MCU_HW_LOCK(lchip,   core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, DMPS_HW_LOCK_GRAND_BIT_3)
#define DMPS_MSG_HW_UNLOCK(lchip, core_id, core_mcu_id) MCU_HW_UNLOCK(lchip, core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, DMPS_HW_LOCK_GRAND_BIT_3)

#define CL73_REG_IO_HW_LOCK(lchip, core_id, core_mcu_id, hss_grp)  MCU_HW_LOCK(lchip, core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, \
                                                                           ((hss_grp == 0) ? DMPS_HW_LOCK_GRAND_BIT_4 : DMPS_HW_LOCK_GRAND_BIT_5))

#define CL73_REG_IO_HW_UNLOCK(lchip, core_id, core_mcu_id, hss_grp) MCU_HW_UNLOCK(lchip, core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, \
                                                                            ((hss_grp == 0) ? DMPS_HW_LOCK_GRAND_BIT_4 : DMPS_HW_LOCK_GRAND_BIT_5))

#define M2C_INTR_HW_LOCK(lchip, core_id, core_mcu_id)   MCU_HW_LOCK(lchip,   core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, DMPS_HW_LOCK_GRAND_BIT_6)
#define M2C_INTR_HW_UNLOCK(lchip, core_id, core_mcu_id) MCU_HW_UNLOCK(lchip, core_id, core_mcu_id, DMPS_HW_LOCK_GRANT_ID, DMPS_HW_LOCK_GRAND_BIT_6)

/* mcu hardware lock end */

struct  sys_usw_mcu_port_attr_s
{
    uint8 mac_en;            /* mac enable config */
    uint8 mac_id;
    uint8 serdes_id;
    uint8 serdes_id2;    /* if 50G and lane swap, serdes_id2 is the second serdes ID, otherwise, this is 0 */
    
    uint8 serdes_num;    /*serdes num of port*/
    uint8 serdes_mode;      /*refer to ctc_chip_serdes_mode_t*/
    uint8 flag;       /* for D2 50G, if serdes lane 0/1 and 2/3 form 50G port, flag is eq to 0;
                                     if serdes lane 2/1 and 0/3 form 50G port, flag is eq to 1; */
    uint8 unidir_en;   /* unidir en config */

    uint8 rsv1;    /* make sure here reserved! */
    uint8 an_en;
    uint8 rsv[6];
};
typedef struct  sys_usw_mcu_port_attr_s sys_usw_mcu_port_attr_t;

enum sys_mcu_serdes_mode_e
{
    SYS_MCU_SERDES_NONE_MODE,     
    SYS_MCU_SERDES_XFI_MODE,      
    SYS_MCU_SERDES_SGMII_MODE,    
    SYS_MCU_SERDES_XSGMII_MODE,   
    SYS_MCU_SERDES_QSGMII_MODE,   
    SYS_MCU_SERDES_XAUI_MODE,     
    SYS_MCU_SERDES_DXAUI_MODE,    
    SYS_MCU_SERDES_XLG_MODE,      
    SYS_MCU_SERDES_CG_MODE,       
    SYS_MCU_SERDES_2DOT5G_MODE,   
    SYS_MCU_SERDES_USXGMII0_MODE, 
    SYS_MCU_SERDES_USXGMII1_MODE, 
    SYS_MCU_SERDES_USXGMII2_MODE, 
    SYS_MCU_SERDES_XXVG_MODE,     
    SYS_MCU_SERDES_LG_MODE,       
    SYS_MCU_SERDES_100BASEFX_MODE,
    SYS_MCU_SERDES_LG_R1_MODE,    
    SYS_MCU_SERDES_CG_R2_MODE,    
    SYS_MCU_SERDES_CCG_R4_MODE,   
    SYS_MCU_SERDES_CDG_R8_MODE,   
    SYS_MCU_SERDES_XLG_R2_MODE,   
    SYS_MCU_SERDES_CG_R1_MODE,    
    SYS_MCU_SERDES_CCG_R2_MODE,   
    SYS_MCU_SERDES_CDG_R4_MODE,   
    SYS_MCU_SERDES_DCCCG_R8_MODE, 
    SYS_MCU_SERDES_PHY_MODE,      
    SYS_MCU_SERDES_RGMII_MODE,
    SYS_MCU_SERDES_XLG_R1_MODE,
    SYS_MCU_MAX_SERDES_MODE
};
typedef enum sys_mcu_serdes_mode_e sys_mcu_serdes_mode_t;
enum sys_mcu_log_event_s
{
    SYS_MCU_LOG_EVENT_0_AN_EN = 0,
    SYS_MCU_LOG_EVENT_1_AN_DIS,
    SYS_MCU_LOG_EVENT_2_LT_EN,
    SYS_MCU_LOG_EVENT_3_AN_GOOD_INTR,
    SYS_MCU_LOG_EVENT_4_AN_NO_HCD,
    SYS_MCU_LOG_EVENT_5_AN_LANE_NUM_NEQ,
    SYS_MCU_LOG_EVENT_6_LT_GOOD_INTR,
    SYS_MCU_LOG_EVENT_7_AN_OK,
    SYS_MCU_LOG_EVENT_8_ANLT_OK,
    SYS_MCU_LOG_EVENT_9_RESATRT_AN_START,
    SYS_MCU_LOG_EVENT_10_RESATRT_AN_END,
    SYS_MCU_LOG_EVENT_11_AN_TMIEOUT,
    SYS_MCU_LOG_EVENT_12_LT_TMIEOUT,    
    SYS_MCU_LOG_EVENT_13_SWITCH_SERDES,
    SYS_MCU_LOG_EVENT_14_REQ_CPU_DYN,
    SYS_MCU_LOG_EVENT_15_REQ_CPU_RELEASE_MAC,
    SYS_MCU_LOG_EVENT_16_RECV_ANLT_INTR,
    SYS_MCU_LOG_EVENT_17_PROC_SYNC_MSG_START,
    SYS_MCU_LOG_EVENT_18_PROC_SYNC_MSG_END,
    SYS_MCU_LOG_EVENT_19_PROC_ASYNC_MSG_START,
    SYS_MCU_LOG_EVENT_20_PROC_ASYNC_MSG_END,
    SYS_MCU_LOG_EVENT_21_RECV_MSG_START,
    SYS_MCU_LOG_EVENT_22_RECV_MSG_END,
    SYS_MCU_LOG_EVENT_23_GET_MAC_RX_STATS_START,
    SYS_MCU_LOG_EVENT_24_GET_MAC_RX_STATS_END,
    SYS_MCU_LOG_EVENT_25_GET_MAC_TX_STATS_START,
    SYS_MCU_LOG_EVENT_26_GET_MAC_TX_STATS_END,
    SYS_MCU_LOG_EVENT_27_POLL_MAC_STATS_START,
    SYS_MCU_LOG_EVENT_28_POLL_MAC_STATS_END,
    SYS_MCU_LOG_EVENT_29_LINK_UP_TMIEOUT,
    SYS_MCU_LOG_EVENT_30_LINK_UP,
    SYS_MCU_LOG_EVENT_31_TIMER_EN,
    SYS_MCU_LOG_EVENT_32_SERDES_POLL_PIN_FAIL,
    SYS_MCU_LOG_EVENT_33_LINK_DOWN,
    SYS_MCU_LOG_EVENT_34_RECV_RX_PAGE_INTR,
    SYS_MCU_LOG_EVENT_35_SYNC_AN_FEC,
    SYS_MCU_LOG_EVENT_36_GET_ANLT_STATE,
    SYS_MCU_LOG_EVENT_37_AN_HCD,
    SYS_MCU_LOG_EVENT_MAX
};
typedef enum sys_mcu_log_event_s sys_mcu_log_event_t;

enum sys_mcu_log_event_type_s
{
    SYS_MCU_LOG_EVENT_0_TYPE_DPORT           = 0,
    SYS_MCU_LOG_EVENT_1_TYPE_DPORT           = 0,
    SYS_MCU_LOG_EVENT_1_TYPE_SERDES_SPEED    = 1,
    SYS_MCU_LOG_EVENT_2_TYPE_FUNC_POS        = 0,
    SYS_MCU_LOG_EVENT_3_TYPE_PSD             = 0,
    SYS_MCU_LOG_EVENT_6_TYPE_INNER_ID        = 0,
    SYS_MCU_LOG_EVENT_6_TYPE_PCS_LANE_BMP    = 1,
    SYS_MCU_LOG_EVENT_6_TYPE_LT_DONE_BMP     = 2,
    SYS_MCU_LOG_EVENT_7_TYPE_PSD             = 0,
    SYS_MCU_LOG_EVENT_8_TYPE_INNER_ID        = 0,
    SYS_MCU_LOG_EVENT_9_TYPE_INNER_ID        = 0,
    SYS_MCU_LOG_EVENT_11_TYPE_INNER_ID       = 0,
    SYS_MCU_LOG_EVENT_12_TYPE_INNER_ID       = 0,
    SYS_MCU_LOG_EVENT_13_TYPE_SERDES_SPEED   = 0,
    SYS_MCU_LOG_EVENT_13_TYPE_FUNC_POS       = 1,
    SYS_MCU_LOG_EVENT_16_TYPE_PSD            = 0,
    SYS_MCU_LOG_EVENT_16_TYPE_INTR_TYPE      = 1,
    SYS_MCU_LOG_EVENT_17_TYPE_MSG_TYPE       = 0,
    SYS_MCU_LOG_EVENT_19_TYPE_MSG_TYPE       = 0,
    SYS_MCU_LOG_EVENT_23_TYPE_MAC_GROUP_ID   = 0,
    SYS_MCU_LOG_EVENT_23_TYPE_STATS_BLOCK_ID = 1,
    SYS_MCU_LOG_EVENT_23_TYPE_MAC_STAT_OP    = 2,
    SYS_MCU_LOG_EVENT_25_TYPE_MAC_GROUP_ID   = 0,
    SYS_MCU_LOG_EVENT_25_TYPE_STATS_BLOCK_ID = 1,
    SYS_MCU_LOG_EVENT_25_TYPE_MAC_STAT_OP    = 2,
    SYS_MCU_LOG_EVENT_29_TYPE_INNER_ID       = 0,
    SYS_MCU_LOG_EVENT_30_TYPE_INNER_ID       = 0,
    SYS_MCU_LOG_EVENT_30_TYPE_PCS_STATUS     = 1,
    SYS_MCU_LOG_EVENT_31_TYPE_TIMER_EN       = 0,
    SYS_MCU_LOG_EVENT_31_TYPE_INNER_ID       = 1,
    SYS_MCU_LOG_EVENT_32_TYPE_PIN            = 0,
    SYS_MCU_LOG_EVENT_32_TYPE_PIN_DATA       = 1,
    SYS_MCU_LOG_EVENT_32_TYPE_EXP_VAL        = 2,
    SYS_MCU_LOG_EVENT_33_TYPE_INNER_ID       = 0,
    SYS_MCU_LOG_EVENT_33_TYPE_PCS_STATUS     = 1,
    SYS_MCU_LOG_EVENT_34_TYPE_PSD            = 0,
    SYS_MCU_LOG_EVENT_34_TYPE_BASE_PAGE      = 1,
    SYS_MCU_LOG_EVENT_34_TYPE_NEXT_PAGE1     = 2,
    SYS_MCU_LOG_EVENT_35_TYPE_INNER_ID       = 0,
    SYS_MCU_LOG_EVENT_36_TYPE_INNER_ID       = 0,
    SYS_MCU_LOG_EVENT_37_TYPE_PSD            = 0,
    SYS_MCU_LOG_EVENT_37_TYPE_IF_MODE        = 1,
    SYS_MCU_LOG_EVENT_37_TYPE_FEC_MODE       = 2,
};
typedef enum sys_mcu_log_event_type_s sys_mcu_log_event_type_t;

enum sys_mcu_log_event_type_string_s
{
    SYS_MCU_LOG_EVENT_TYPE_STR_NONE          = 0,
    SYS_MCU_LOG_EVENT_TYPE_STR_DPORT,
    SYS_MCU_LOG_EVENT_TYPE_STR_SERDES_SPEED,
    SYS_MCU_LOG_EVENT_TYPE_STR_PSD,
    SYS_MCU_LOG_EVENT_TYPE_STR_INNER_ID,
    SYS_MCU_LOG_EVENT_TYPE_STR_PCS_LANE_BMP,
    SYS_MCU_LOG_EVENT_TYPE_STR_LT_DONE_BMP,
    SYS_MCU_LOG_EVENT_TYPE_STR_MSG_TYPE,
    SYS_MCU_LOG_EVENT_TYPE_STR_INTR_TYPE,
    SYS_MCU_LOG_EVENT_TYPE_STR_MAC_GROUP_ID,
    SYS_MCU_LOG_EVENT_TYPE_STR_STATS_BLOCK_ID,
    SYS_MCU_LOG_EVENT_TYPE_STR_MAC_STAT_OP,
    SYS_MCU_LOG_EVENT_TYPE_STR_TIMER_EN,
    SYS_MCU_LOG_EVENT_TYPE_STR_FUNC_POS,
    SYS_MCU_LOG_EVENT_TYPE_STR_PIN,
    SYS_MCU_LOG_EVENT_TYPE_STR_PIN_DATA,
    SYS_MCU_LOG_EVENT_TYPE_STR_EXP_VAL,
    SYS_MCU_LOG_EVENT_TYPE_STR_PCS_STATUS,
    SYS_MCU_LOG_EVENT_TYPE_STR_BASE_PAGE,
    SYS_MCU_LOG_EVENT_TYPE_STR_NEXT_PAGE1,
    SYS_MCU_LOG_EVENT_TYPE_STR_IF_MODE,
    SYS_MCU_LOG_EVENT_TYPE_STR_FEC_MODE,
    SYS_MCU_LOG_EVENT_TYPE_STR_MAX
};
typedef enum sys_mcu_log_event_type_string_s sys_mcu_log_event_type_string_t;

#define CTC_SERDES_MODE_TO_SYS_MCU_SERDES_MODE(ctc_mode, mcu_mode)     \
    switch (ctc_mode)                                                  \
    {                                                                  \
        case CTC_CHIP_SERDES_NONE_MODE:                                \
            mcu_mode = SYS_MCU_SERDES_NONE_MODE;                       \
            break;                                                     \
        case CTC_CHIP_SERDES_XFI_MODE:                                 \
            mcu_mode = SYS_MCU_SERDES_XFI_MODE;                        \
            break;                                                     \
        case CTC_CHIP_SERDES_SGMII_MODE:                               \
            mcu_mode = SYS_MCU_SERDES_SGMII_MODE;                      \
            break;                                                     \
        case CTC_CHIP_SERDES_XSGMII_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_XSGMII_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_QSGMII_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_QSGMII_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_XAUI_MODE:                                \
            mcu_mode = SYS_MCU_SERDES_XAUI_MODE;                       \
            break;                                                     \
        case CTC_CHIP_SERDES_DXAUI_MODE:                               \
            mcu_mode = SYS_MCU_SERDES_DXAUI_MODE;                      \
            break;                                                     \
        case CTC_CHIP_SERDES_XLG_MODE:                                 \
            mcu_mode = SYS_MCU_SERDES_XLG_MODE;                        \
            break;                                                     \
        case CTC_CHIP_SERDES_CG_MODE:                                  \
            mcu_mode = SYS_MCU_SERDES_CG_MODE;                         \
            break;                                                     \
        case CTC_CHIP_SERDES_2DOT5G_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_2DOT5G_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_USXGMII0_MODE:                            \
            mcu_mode = SYS_MCU_SERDES_USXGMII0_MODE;                   \
            break;                                                     \
        case CTC_CHIP_SERDES_USXGMII1_MODE:                            \
            mcu_mode = SYS_MCU_SERDES_USXGMII1_MODE;                   \
            break;                                                     \
        case CTC_CHIP_SERDES_USXGMII2_MODE:                            \
            mcu_mode = SYS_MCU_SERDES_USXGMII2_MODE;                   \
            break;                                                     \
        case CTC_CHIP_SERDES_XXVG_MODE:                                \
            mcu_mode = SYS_MCU_SERDES_XXVG_MODE;                       \
            break;                                                     \
        case CTC_CHIP_SERDES_LG_MODE:                                  \
            mcu_mode = SYS_MCU_SERDES_LG_MODE;                         \
            break;                                                     \
        case CTC_CHIP_SERDES_100BASEFX_MODE:                           \
            mcu_mode = SYS_MCU_SERDES_100BASEFX_MODE;                  \
            break;                                                     \
        case CTC_CHIP_SERDES_LG_R1_MODE:                               \
            mcu_mode = SYS_MCU_SERDES_LG_R1_MODE;                      \
            break;                                                     \
        case CTC_CHIP_SERDES_CG_R2_MODE:                               \
            mcu_mode = SYS_MCU_SERDES_CG_R2_MODE;                      \
            break;                                                     \
        case CTC_CHIP_SERDES_CCG_R4_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_CCG_R4_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_CDG_R8_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_CDG_R8_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_XLG_R2_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_XLG_R2_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_CG_R1_MODE:                               \
            mcu_mode = SYS_MCU_SERDES_CG_R1_MODE;                      \
            break;                                                     \
        case CTC_CHIP_SERDES_CCG_R2_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_CCG_R2_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_CDG_R4_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_CDG_R4_MODE;                     \
            break;                                                     \
        case CTC_CHIP_SERDES_DCCCG_R8_MODE:                            \
            mcu_mode = SYS_MCU_SERDES_DCCCG_R8_MODE;                   \
            break;                                                     \
        case CTC_CHIP_SERDES_PHY_MODE:                                 \
            mcu_mode = SYS_MCU_SERDES_PHY_MODE;                        \
            break;                                                     \
        case CTC_CHIP_SERDES_RGMII_MODE:                               \
            mcu_mode = SYS_MCU_SERDES_RGMII_MODE;                      \
            break;                                                     \
        case CTC_CHIP_SERDES_XLG_R1_MODE:                              \
            mcu_mode = SYS_MCU_SERDES_XLG_R1_MODE;                     \
            break;                                                     \
        default:                                                       \
            break;                                                     \
    }

#define SYS_MCU_SERDES_MODE_TO_CTC_SERDES_MODE(mcu_mode, ctc_mode)     \
    switch (mcu_mode)                                                  \
    {                                                                  \
        case SYS_MCU_SERDES_NONE_MODE:                                 \
            ctc_mode = CTC_CHIP_SERDES_NONE_MODE;                      \
            break;                                                     \
        case SYS_MCU_SERDES_XFI_MODE:                                  \
            ctc_mode = CTC_CHIP_SERDES_XFI_MODE;                       \
            break;                                                     \
        case SYS_MCU_SERDES_SGMII_MODE:                                \
            ctc_mode = CTC_CHIP_SERDES_SGMII_MODE;                     \
            break;                                                     \
        case SYS_MCU_SERDES_XSGMII_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_XSGMII_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_QSGMII_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_QSGMII_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_XAUI_MODE:                                 \
            ctc_mode = CTC_CHIP_SERDES_XAUI_MODE;                      \
            break;                                                     \
        case SYS_MCU_SERDES_DXAUI_MODE:                                \
            ctc_mode = CTC_CHIP_SERDES_DXAUI_MODE;                     \
            break;                                                     \
        case SYS_MCU_SERDES_XLG_MODE:                                  \
            ctc_mode = CTC_CHIP_SERDES_XLG_MODE;                       \
            break;                                                     \
        case SYS_MCU_SERDES_CG_MODE:                                   \
            ctc_mode = CTC_CHIP_SERDES_CG_MODE;                        \
            break;                                                     \
        case SYS_MCU_SERDES_2DOT5G_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_2DOT5G_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_USXGMII0_MODE:                             \
            ctc_mode = CTC_CHIP_SERDES_USXGMII0_MODE;                  \
            break;                                                     \
        case SYS_MCU_SERDES_USXGMII1_MODE:                             \
            ctc_mode = CTC_CHIP_SERDES_USXGMII1_MODE;                  \
            break;                                                     \
        case SYS_MCU_SERDES_USXGMII2_MODE:                             \
            ctc_mode = CTC_CHIP_SERDES_USXGMII2_MODE;                  \
            break;                                                     \
        case SYS_MCU_SERDES_XXVG_MODE:                                 \
            ctc_mode = CTC_CHIP_SERDES_XXVG_MODE;                      \
            break;                                                     \
        case SYS_MCU_SERDES_LG_MODE:                                   \
            ctc_mode = CTC_CHIP_SERDES_LG_MODE;                        \
            break;                                                     \
        case SYS_MCU_SERDES_100BASEFX_MODE:                            \
            ctc_mode = CTC_CHIP_SERDES_100BASEFX_MODE;                 \
            break;                                                     \
        case SYS_MCU_SERDES_LG_R1_MODE:                                \
            ctc_mode = CTC_CHIP_SERDES_LG_R1_MODE;                     \
            break;                                                     \
        case SYS_MCU_SERDES_CG_R2_MODE:                                \
            ctc_mode = CTC_CHIP_SERDES_CG_R2_MODE;                     \
            break;                                                     \
        case SYS_MCU_SERDES_CCG_R4_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_CCG_R4_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_CDG_R8_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_CDG_R8_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_XLG_R2_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_XLG_R2_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_CG_R1_MODE:                                \
            ctc_mode = CTC_CHIP_SERDES_CG_R1_MODE;                     \
            break;                                                     \
        case SYS_MCU_SERDES_CCG_R2_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_CCG_R2_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_CDG_R4_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_CDG_R4_MODE;                    \
            break;                                                     \
        case SYS_MCU_SERDES_DCCCG_R8_MODE:                             \
            ctc_mode = CTC_CHIP_SERDES_DCCCG_R8_MODE;                  \
            break;                                                     \
        case SYS_MCU_SERDES_PHY_MODE:                                  \
            ctc_mode = CTC_CHIP_SERDES_PHY_MODE;                       \
            break;                                                     \
        case SYS_MCU_SERDES_RGMII_MODE:                                \
            ctc_mode = CTC_CHIP_SERDES_RGMII_MODE;                     \
            break;                                                     \
        case SYS_MCU_SERDES_XLG_R1_MODE:                               \
            ctc_mode = CTC_CHIP_SERDES_XLG_R1_MODE;                    \
            break;                                                     \
        default:                                                       \
            break;                                                     \
    }

extern int32 sys_usw_mcu_chip_read(uint8 lchip, uint32 offset, uint32* p_value);
extern int32 sys_usw_mcu_chip_write(uint8 lchip, uint32 offset, uint32 value);
extern int32 sys_usw_mac_mcu_init(uint8 lchip);
extern int32 sys_usw_mac_set_mcu_enable(uint8 lchip, uint32 enable);
extern int32 sys_usw_mac_get_mcu_enable(uint8 lchip, uint32* enable);
extern int32 sys_usw_mac_set_mcu_port_enable(uint8 lchip, uint32 gport, uint32 enable);
extern int32 sys_usw_mac_get_mcu_port_enable(uint8 lchip, uint32 gport, uint32* enable);

#ifdef __cplusplus
}
#endif

#endif
